Leading-Zero Anticipator (LZA) in the IBM RISC System/6000 Floating-Point Execution Unit
نویسندگان
چکیده
This paper presents a novel technique used in the multiply-add-fused (MAF) unit of the IBM RlSC System/6000* (RS/6000) processor for normalizing the floating-point results. Unlike the conventional procedures applied thus far, the so-called leading-zero anticipator (LZA) of the RS/SOOO carries out processing of the leading zeros and ones in parallel with floating-point addition. Therefore, the new circuitry reduces the total latency of the MAF unit by enabling the normalization and addition to take place in a single cycle.
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Comments on “Leading-Zero Anticipatory Logic for High-Speed Floating Point Addition”
I have read with a great interest the above article by H. Suzuki et al. I am familiar with their work, and I found their approach interesting. The idea used to simplify the leading zero anticipator (LZA) I found innovative and an improvement over the one used in the IBM RS/6000. One of the critical parts of their LZA circuit is the leading zero detector (referred as leading zero counter in the ...
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This paper describes a new leading-zero anticipatory (LZA) logic for high-speed floating-point addition (FADD). This logic carries out the pre-decoding for normalization concurrently with addition for the significand. It also performs the shift operation of normalization in parallel with the rounding operation. The use of simple Boolean algebra allows the proposed logic to be constructed from a...
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ورودعنوان ژورنال:
- IBM Journal of Research and Development
دوره 34 شماره
صفحات -
تاریخ انتشار 1990